Register File 4×4

Official

Digital

·

Generic

·

Curated by CircuitSim

Register File 4×4 schematic symbol
Details

Manufacturer

Generic


Part number


Pins

20


Used in

No circuits


Added

Sep 2026

About this component

Four-register by four-bit register file with two independent asynchronous read ports and one synchronous write port. WE captures WD0–WD3 into WA1:WA0 on the rising CLK edge; initial register values are editable.

Parameters

Logic levels
2 parameters
ParameterNameDescriptionDefault

VTH

Input threshold

Voltage at or above which an input is interpreted as logic high.

2.5 V

VHIGH

High output voltage

Voltage driven for a logic-high output.

5 V

Timing
1 parameter
ParameterNameDescriptionDefault

TPD

Propagation delay

Clock-to-state transition delay for each ideal storage bit.

1n s

Initial contents
4 parameters
ParameterNameDescriptionDefault

IR0

Initial register 0

Deterministic unsigned four-bit power-up value for register 0; bit 0 maps to QA0/QB0.

0

IR1

Initial register 1

Deterministic unsigned four-bit power-up value for register 1; bit 0 maps to QA0/QB0.

0

IR2

Initial register 2

Deterministic unsigned four-bit power-up value for register 2; bit 0 maps to QA0/QB0.

0

IR3

Initial register 3

Deterministic unsigned four-bit power-up value for register 3; bit 0 maps to QA0/QB0.

0

Pins

Pins
20 pins
NumberNameDescription

1

WA0

Write-address bit 0 and least-significant write-address bit.

2

WA1

Write-address bit 1.

3

WD0

Write-data bit 0 and least-significant data bit.

4

WD1

Write-data bit 1.

5

WD2

Write-data bit 2.

6

WD3

Write-data bit 3 and most-significant data bit.

7

WE

Active-high write enable sampled on the rising clock edge.

8

CLK

Rising-edge write clock.

9

RA0

Read-port A address bit 0 and least-significant address bit.

10

RA1

Read-port A address bit 1.

11

RB0

Read-port B address bit 0 and least-significant address bit.

12

RB1

Read-port B address bit 1.

13

QA0

Read-port A data bit 0 and least-significant data bit.

14

QA1

Read-port A data bit 1.

15

QA2

Read-port A data bit 2.

16

QA3

Read-port A data bit 3 and most-significant data bit.

17

QB0

Read-port B data bit 0 and least-significant data bit.

18

QB1

Read-port B data bit 1.

19

QB2

Read-port B data bit 2.

20

QB3

Read-port B data bit 3 and most-significant data bit.

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