CMOS Electrical Inverter
Digital
·
Generic
·
Curated by CircuitSim
Details
Manufacturer
Generic
Part number
—
Pins
4
Used in
No circuits
Added
Sep 2026
About this component
Supply-aware generic CMOS-family teaching inverter with near-zero static input loading, finite input capacitance, output resistance, propagation delay, rail offsets, output capacitance, and quiescent current. It is an educational family model, not a specific 74HC-series part.
Parameters
Logic levels and noise margins
4 parameters
VIL
Maximum low input voltage
Family VIL limit used with VIH to define the switching midpoint and low-state noise margin.
1.5 V
VIH
Minimum high input voltage
Family VIH limit used with VIL to define the switching midpoint and high-state noise margin.
3.5 V
VOH_DROP
Unloaded high-level drop
Voltage subtracted from VCC before high-state loading.
0.02 V
VOL_OFFSET
Unloaded low-level offset
Baseline low-output voltage before sink-current loading.
0.02 V
Electrical loading
6 parameters
ROUT_H
High-state output resistance
Thevenin resistance while sourcing a logic high.
50 ohm
ROUT_L
Low-state output resistance
Thevenin resistance while sinking a logic low.
35 ohm
RIN_P
Input-to-VCC leakage resistance
Simplified CMOS static leakage path from VCC to IN.
1T ohm
RIN_N
Input-to-GND leakage resistance
Simplified CMOS static leakage path from IN to GND.
1T ohm
CIN
Input capacitance
Capacitive load presented at IN.
5p F
COUT
Internal output capacitance
Internal output capacitance added to external loads.
3p F
Timing and power
2 parameters
TPD
Propagation delay
Approximate input-to-output 50% delay before external load effects.
8n s
IQ
Quiescent supply current
Static current drawn from VCC to GND.
1u A
Pins
Pins
4 pins
1
IN
CMOS-family logic input with near-zero static leakage and finite capacitance.
2
OUT
Inverted output with finite high- and low-state resistance.
3
VCC
Positive logic supply; use a current probe here for supply-current and power lessons.
4
GND
Logic-supply reference.
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