Timed Buffer
Digital
·
Generic
·
Curated by CircuitSim
Details
Manufacturer
Generic
Part number
—
Pins
2
Used in
No circuits
Added
Sep 2026
About this component
Non-inverting thresholded logic block with common and edge-specific propagation delays for timing, hazard, and skew lessons. Behavioral voltage output: drive strength and load-dependent rise/fall are not modeled. This primitive does not model setup/hold time or metastability.
Parameters
Logic levels
2 parameters
VHIGH
High output voltage
Voltage driven for logic high.
5 V
VTH
Input threshold
Voltage above which IN is interpreted as high.
2.5 V
Timing
3 parameters
PROPAGATIONDELAY
Common propagation delay
Delay added to both output edges.
0 s
RISEDELAY
Additional rise delay
Additional input-to-output delay for a low-to-high output transition.
1e-9 s
FALLDELAY
Additional fall delay
Additional input-to-output delay for a high-to-low output transition.
1e-9 s
Pins
Pins
2 pins
1
IN
Logic input. Voltages above VTH are interpreted as high.
2
OUT
Non-inverted thresholded logic output.
Public circuits using this component
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