New Circuit

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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X_S1 N2 0 N3 TDSW1_1bcd2ff9 OnTime=0.5 OffTime=1
X_S2 N2 0 N5 TDSW1_1bcd2ff9 OnTime=0.5 OffTime=1
X_S3 N2 0 N4 TDSW1_1bcd2ff9 OnTime=0.5 OffTime=1
X_U1 N7 N5 N3 N4 N6 N7 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
vV1 N2 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
APROBE_DP1 [N6] [d_DP1] AMODEL_DP1
APROBE_DP2 [N7] [d_DP2] AMODEL_DP2

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* Models and supporting definitions follow
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.SUBCKT TDSW1_1bcd2ff9 ON OFF COMMON PARAMS: OnTime=0.5 OffTime=1
    BSTATE STATE 0 V={((OnTime < OffTime) ? ((time > OnTime) ? ((time > OffTime) ? 0 : 1) : 0) : ((time > OffTime) ? ((time > OnTime) ? 1 : 0) : 1))}
    BSTATE_INV STATE_INV 0 V={1-V(STATE)}
    S_ON ON COMMON STATE 0 TDSW1_1bcd2ff9_SW
    S_OFF OFF COMMON STATE_INV 0 TDSW1_1bcd2ff9_SW
    .MODEL TDSW1_1bcd2ff9_SW SW(Ron=10m Roff=1Meg Vt=0.25 Vh=0.2495)
.ENDS TDSW1_1bcd2ff9
* DigitalDFlipFlop_79c3a797 normalized for ngspice-web: analog bridges replace unsupported source polarity helpers.
.subckt DigitalDFlipFlop_79c3a797 1 2 3 4 5 6 params: NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1e-9 FallDelay=1e-9 VTH=2.5 VHIGH=5
    BD_INACTIVE D_INACTIVE 0 V = 0
    RDATA_DEFAULT 1 D_INACTIVE 1G
    BSET_INACTIVE SET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    BRESET_INACTIVE RESET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    RSET_DEFAULT 3 SET_INACTIVE 1G
    RRESET_DEFAULT 4 RESET_INACTIVE 1G
    BCLK_POL CLK_POL 0 V = { (NegativeEdgeClock > 0.5) ? ((V(2) > VTH) ? 0 : VHIGH) : V(2) }
    BSET_POL SET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(3) > VTH) ? 0 : VHIGH) : V(3) }
    BRESET_POL RESET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(4) > VTH) ? 0 : VHIGH) : V(4) }
    .model DigitalDFlipFlop_79c3a797_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model DigitalDFlipFlop_79c3a797_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model DigitalDFlipFlop_79c3a797_CORE d_dff(clk_delay={ClkDelay} set_delay={SetDelay} reset_delay={ResetDelay} ic={Ic} rise_delay={RiseDelay} fall_delay={FallDelay})
    AD [1] [d_data] DigitalDFlipFlop_79c3a797_A2D
    ACLK [CLK_POL] [d_clk] DigitalDFlipFlop_79c3a797_A2D
    ASET [SET_POL] [d_set] DigitalDFlipFlop_79c3a797_A2D
    ARESET [RESET_POL] [d_reset] DigitalDFlipFlop_79c3a797_A2D
    AFF d_data d_clk d_set d_reset d_q d_nq DigitalDFlipFlop_79c3a797_CORE
    AQ [d_q] [5] DigitalDFlipFlop_79c3a797_D2A
    ANQ [d_nq] [6] DigitalDFlipFlop_79c3a797_D2A
.ends DigitalDFlipFlop_79c3a797
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)

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* Simulation settings
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.tran 100u 100m 0
.save v(x_S1.state) v(x_S2.state) v(x_S3.state)
.end