CMOS Inverter

Complementary transistors switch the output between the supply rails while drawing almost no steady-state current.

Circuit operation

The p-channel device connects the output to the positive rail for a low input. The n-channel device connects it to ground for a high input. The two gate terminals share Vin. Compare the green input with the red output; Isupply is positive for current delivered by VDD.

Expected behavior

$$V_{\mathrm{out}}\approx V_{DD}-V_{\mathrm{in}}$$ $$P_{\mathrm{static}}=V_{DD}I_{DD}$$

For valid rail-level inputs, Vout approaches 5 V or 0 V and the supply current is very small. Near the switching point, both devices can conduct. The voltage equation describes the two logic endpoints, not a linear amplifier transfer law.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 4.0 ms with a maximum step of 1.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 950 µs; compare the time scale of the response. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The CMOS models use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.