CMOS Transmission Gate

Pass an analog signal through parallel n-channel and p-channel switches driven by complementary controls.

Circuit operation

SW1P and SW1N share the signal path. Enable drives the n-channel gate directly and the p-channel gate through a CMOS inverter. Their body connections are explicitly tied to VDD and ground, allowing bidirectional signals within the supply rails.

Expected behavior

$$R_{\mathrm{on}}=R_n\parallel R_p$$ $$V_o=V_i\frac{R_L}{R_L+R_{\mathrm{on}}}$$

When Enable is high, Vout follows the 0.5–4.5 V sine wave. When Enable is low, the load pulls the output toward ground. The two transistor types complement each other: n-channel conduction is strongest near the lower rail, p-channel conduction near the upper rail.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 4.0 ms with a maximum step of 1.00 µs. Use the middle of settled plateaus for logic comparisons and the time-axis cursors for delays.

Try a change

Set V1 period to 2 ms and pulse width to 950 µs; compare the time scale of the response. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The 5 V circuits use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.