CMOS Multiplexer

Two complementary transmission gates select one of two analog inputs.

Circuit operation

Two transmission gates share the output. Complementary controls enable exactly one path in each steady state. Input A is a 0.5–4.5 V sine wave; input B is a 1 V reference. The 2 nF output capacitance gives switching transients a physical load.

Expected behavior

$$V_o=\begin{cases}V_A,&S=1\\V_B,&S=0\end{cases}$$ $$\tau\approx R_{\mathrm{on}}C_L$$

Compare the selected sine wave with the flat 1 V intervals. Short edge disturbances come from charge sharing and the finite complementary-control delay; allow settling before evaluating a selected value.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 4.0 ms with a maximum step of 1.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 950 µs; compare the time scale of the response. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The CMOS models use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.