Leading-Edge Detector

Compare a logic input with its delayed version to produce a brief positive pulse only at a rising edge.

Circuit operation

The first two inverters and R1–C1 make a delayed copy of the input. A transistor-level NOR combines the inverted immediate input with the delayed noninverted input. Only a rising input creates the condition for a high output.

Expected behavior

$$Y=A\land\overline{A_{\mathrm{delayed}}}$$ $$t_{\mathrm{pulse}}\approx R_1C_1\ln2$$

The red trace shows a positive pulse of approximately 69 µs at each rising edge. The falling edge should not produce a comparable pulse. CL is a 2 nF output load; device resistance and threshold shift the precise pulse width.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 4.0 ms with a maximum step of 1.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 950 µs; compare the time scale of the response. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The CMOS models use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.