CMOS Master-Slave Flip-Flop

Two transmission-gate latches on opposite clock phases capture data on a rising clock edge.

Circuit operation

The master latch is transparent while Clock is low. The slave latch is transparent while Clock is high. Each latch uses a forward transmission gate, two inverters, and a feedback transmission gate.

Expected behavior

$$Q(t_k^+)=D(t_k^-)$$ $$t_k:\ \mathrm{rising\ clock\ edge}$$

Compare D, Master, Clock, and Q. Master follows D during the low clock phase; Q takes that stored value at the rising edge and holds it for the rest of the cycle. The input period differs from the clock period to expose the capture behavior. Finite gate delays mean setup and hold intervals still matter.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 4.0 ms with a maximum step of 1.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 950 µs; compare the time scale of the response. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The CMOS models use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.