Johnson Counter / Decade Counter

Feed the inverted last bit into a five-stage shift register to generate ten repeating states.

Circuit operation

Five edge-triggered storage stages shift their true and complementary outputs to the next stage. The last stage feeds its complement back to the first, creating a twisted ring. All stages share the same clock.

Expected behavior

$$Q_0^{next}=\overline{Q_4}$$ $$N_{states}=2n=10\quad(n=5)$$

From all zeros, ones fill the register, then zeros fill it: ten distinct states repeat. Each output has a period of ten clock cycles. This sequence differs from the four-bit BCD output of a decimal counter.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 22.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 998 µs. State changes follow the slower clock while the logic relationship remains the same. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.