JK Flip-Flop
Digital
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Generic
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Curated by CircuitSim
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Used in 1 public circuit
About this component
JK flip-flop with set, reset, clock polarity, initial state, and propagation delay parameters.
Parameters
Logic options
5 parameters
ACTIVELOWSETRESET
Active-low set/reset
Set to 1 to invert the SET and RESET inputs.
0
NEGATIVEEDGECLOCK
Negative-edge clock
Set to 1 to trigger on the falling clock edge.
0
INITIALSTATE
Initial state
Initial Q state.
0
VTH
Input threshold
Analog threshold used to interpret logic inputs.
2.5 V
VHIGH
High output voltage
Analog voltage driven for logic high outputs.
5 V
Timing
5 parameters
CLOCKDELAY
Clock delay
Clock-to-output delay.
1e-9 s
SETDELAY
Set delay
Set-to-output delay.
1e-9 s
RESETDELAY
Reset delay
Reset-to-output delay.
1e-9 s
RISEDELAY
Rise delay
Output low-to-high propagation delay.
1e-9 s
FALLDELAY
Fall delay
Output high-to-low propagation delay.
1e-9 s
Pins
Pins
7 pins
1
J
J input.
2
K
K input.
3
CLK
Clock input.
4
SET
Set input.
5
RESET
Reset input.
6
Q
Q output.
7
~Q
Complementary Q output.
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