Divide-by-3

A two-stage state machine cycles through three states to divide the clock frequency by three.

Circuit operation

Two JK devices are wired as D storage: each K input receives the complement of its J input. The first next-state input is NOR(Q0,Q1), and the second copies Q0.

Expected behavior

$$\begin{gathered}D_0=\overline{Q_0+Q_1}\\D_1=Q_0\end{gathered}$$ $$f_o=f_{clk}/3$$

The state sequence Q1 Q0 is 00 → 01 → 10 → 00. Q1 is high for one of the three clock intervals, so the divided output has a one-third duty ratio. The unused 11 state returns to 10 and then rejoins the cycle.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 26.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 998 µs. State changes follow the slower clock while the logic relationship remains the same. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.