Divide-by-2

A toggling JK flip-flop produces one output cycle for every two clock cycles.

Circuit operation

J and K are tied high. The falling-edge JK flip-flop toggles once per input clock cycle. Qbar drives only a light load; Q is the divided output.

Expected behavior

$$Q_{next}=\overline Q$$ $$f_o=f_{clk}/2$$

Two falling input edges complete one output cycle. The output duty ratio approaches 50% even if the input pulse width changes, provided both clock levels last long enough to be recognized.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 998 µs. State changes follow the slower clock while the logic relationship remains the same. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.