Ternary Logic Inverter

Threshold-separated CMOS devices and a resistive midpoint implement the three levels 0 V, 2.5 V, and 5 V.

Circuit operation

A p-channel threshold of −3 V and an n-channel threshold of +3 V leave a middle input interval where both transistors are off. Two 100 kΩ resistors establish the intermediate output near half the supply.

Expected behavior

$$V_M\approx\frac{V_{DD}}2=2.5\,\mathrm{V}$$ $$0\mapsto5,\quad2.5\mapsto2.5,\quad5\mapsto0$$

As the input sweeps, the output moves through high, middle, and low regions. This is a ratioed illustrative ternary circuit, not a standard binary CMOS gate. RL slightly loads the resistor-defined middle level, and real threshold variation would change the widths of the three regions.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 6.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 6 ms and fall time to 3 ms; the voltage transfer characteristic is unchanged while the time scale expands. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The CMOS models use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.