Edge-Triggered D Flip-Flop

Capture a data bit at each rising clock edge and demonstrate an asynchronous reset between edges.

Circuit operation

Two opposite-phase D latches implement a rising-edge D flip-flop. RESET connects to both asynchronous reset inputs. Its pulse is deliberately placed between clock edges.

Expected behavior

$$Q(t_k^+)=D(t_k^-)$$ $$RESET=1\Rightarrow Q=0$$

Compare D and Q at rising Clock edges. Q also clears immediately during Reset, without waiting for a clock edge. Do not change data exactly on a clock edge when exploring setup and hold behavior; the model does not simulate analog metastability.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 2 ms and pulse width to 998 µs. State changes follow the slower clock while the logic relationship remains the same. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.