D Latch
Digital
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Generic
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Curated by CircuitSim
About this component
Level-sensitive D latch with enable, set and reset inputs, and true and complementary outputs.
Parameters
Advanced
7 parameters
RISE_DELAY
Rise delay
Time to wait before returning an output after the output goes from low to high.
1e-9 s
FALL_DELAY
Fall delay
Time to wait before returning an output after the output goes from high to low.
1e-9 s
DATA_DELAY
Data delay
Time to wait before accepting a data signal after the signal arrives.
1e-9 s
ENABLE_DELAY
Enable delay
Time to wait before accepting an enable signal after the signal arrives.
1e-9 s
SET_DELAY
Set delay
Time to wait before accepting a set signal after the signal arrives.
1e-9 s
RESET_DELAY
Reset delay
Time to wait before accepting a reset signal after the signal arrives.
1e-9 s
IC
Initial output state
Initial Q output state: 0 starts low and 1 starts high.
0
Pins
Pins
6 pins
1
D
Data input.
2
EN
Enable input.
3
Q
True output.
4
RESET
Asynchronous reset input.
5
SET
Asynchronous set input.
6
~Q
Complementary output.
Public circuits using this component
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