JK Flip-Flop Set-Reset Operating Point

Application

This circuit shows the JK flip-flop with explicit logic constants on every input so the output state can be inspected without ambiguous floating controls.

Schematic Organization

J, CLK, and K enter from the left. SET is driven from above, RESET from below, and Q plus Qn drive light loads and digital probes on the right.

Expected Behavior

SET is held high and RESET is held low for the default active-high set/reset configuration, so Q should resolve high and Qn should resolve low.

Suggested Experiments

Set SET to 0, then change J, K, and CLK to explore the stored state. Try setting Active-low set/reset to 1 and update the SET/RESET source states accordingly.

Featured Component

The featured component preserves the seven-pin JK flip-flop symbol and exposes timing, threshold, output-level, and polarity parameters for more detailed digital experiments.