6_2_1_Asynchroner_Frequenzteiler_Lsg

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_DG1 N1 DigitalClock_4e731c5d Frequency=1 Duty=50 Delay=0
X_U1 N6 N1 NC_1 0 N2 N6 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U2 N7 N2 NC_3 NC_2 N3 N7 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U3 N8 N3 NC_5 NC_4 N4 N8 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U4 N9 N4 NC_7 NC_6 N5 N9 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U5 N5 N4 N3 N2 CS_HEX7SEG_DISPLAY InputThreshold=2.5 HighVoltage=5
APROBE_Clk [N1] [d_Clk] AMODEL_Clk
APROBE_Q1 [N2] [d_Q1] AMODEL_Q1
APROBE_Q2 [N3] [d_Q2] AMODEL_Q2
APROBE_Q3 [N4] [d_Q3] AMODEL_Q3
APROBE_Q4 [N5] [d_Q4] AMODEL_Q4

**************************************************
* Models and supporting definitions follow
**************************************************
.subckt DigitalClock_4e731c5d OUT PARAMS: Frequency=1000 Duty=50 Delay=0
    .param period={1/Frequency}
    .param pulseWidth={Duty*0.01/Frequency}
    VCLK OUT 0 PULSE(0 5 {Delay} 1n 1n {pulseWidth} {period})
.ENDS DigitalClock_4e731c5d
* DigitalDFlipFlop_79c3a797 normalized for ngspice-web: analog bridges replace unsupported source polarity helpers.
.subckt DigitalDFlipFlop_79c3a797 1 2 3 4 5 6 params: NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1e-9 FallDelay=1e-9 VTH=2.5 VHIGH=5
    BD_INACTIVE D_INACTIVE 0 V = 0
    RDATA_DEFAULT 1 D_INACTIVE 1G
    BSET_INACTIVE SET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    BRESET_INACTIVE RESET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    RSET_DEFAULT 3 SET_INACTIVE 1G
    RRESET_DEFAULT 4 RESET_INACTIVE 1G
    BCLK_POL CLK_POL 0 V = { (NegativeEdgeClock > 0.5) ? ((V(2) > VTH) ? 0 : VHIGH) : V(2) }
    BSET_POL SET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(3) > VTH) ? 0 : VHIGH) : V(3) }
    BRESET_POL RESET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(4) > VTH) ? 0 : VHIGH) : V(4) }
    .model DigitalDFlipFlop_79c3a797_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model DigitalDFlipFlop_79c3a797_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model DigitalDFlipFlop_79c3a797_CORE d_dff(clk_delay={ClkDelay} set_delay={SetDelay} reset_delay={ResetDelay} ic={Ic} rise_delay={RiseDelay} fall_delay={FallDelay})
    AD [1] [d_data] DigitalDFlipFlop_79c3a797_A2D
    ACLK [CLK_POL] [d_clk] DigitalDFlipFlop_79c3a797_A2D
    ASET [SET_POL] [d_set] DigitalDFlipFlop_79c3a797_A2D
    ARESET [RESET_POL] [d_reset] DigitalDFlipFlop_79c3a797_A2D
    AFF d_data d_clk d_set d_reset d_q d_nq DigitalDFlipFlop_79c3a797_CORE
    AQ [d_q] [5] DigitalDFlipFlop_79c3a797_D2A
    ANQ [d_nq] [6] DigitalDFlipFlop_79c3a797_D2A
.ends DigitalDFlipFlop_79c3a797
.func CS_HEX7SEG_CODE(va,vb,vc,vd,vth) (((va>vth)?1:0)+2*((vb>vth)?1:0)+4*((vc>vth)?1:0)+8*((vd>vth)?1:0))
.func CS_HEX7SEG_MATCH(code,target) ((abs(code-target)<0.5)?1:0)
.subckt CS_HEX7SEG_DISPLAY IND INC INB INA PARAMS: InputThreshold=2.5 HighVoltage=5
    BSEG_A seg_a 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),7)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
    BSEG_B seg_b 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),1)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),7)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13))
    BSEG_C seg_c 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),1)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),7)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13))
    BSEG_D seg_d 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14))
    BSEG_E seg_e 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
    BSEG_F seg_f 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
    BSEG_G seg_g 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
.ends CS_HEX7SEG_DISPLAY
.model AMODEL_Clk adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q1 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q2 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q3 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q4 adc_bridge(in_low=3.3 in_high=3.3)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.options noopalter
.tran 2m 1e12 0 2m
.save v(x_U5.seg_a) v(x_U5.seg_b) v(x_U5.seg_c) v(x_U5.seg_d) v(x_U5.seg_e) v(x_U5.seg_f) v(x_U5.seg_g)
.end