6_1_5_Toggle_Flipflop (Copy)

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
* net label Clk joins Clk::component:node-3:OUT NET_006::component:node-4:2
X_DCT1 NC_1 0 TOGGLEABLE_DIGITAL_CONSTANT state=0 logicLow=0 logicHigh=5
X_DG1 N5 DigitalClock_4e731c5d Frequency=10 Duty=50 Delay=0
X_LED2 N7 0 LED_VIRTUAL_b2f33485 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
X_LED3 N3 0 LED_VIRTUAL_b2f33485 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
aU1 N6 N5 NC_3 NC_2 N7 NC_4 DigitalTFlipFlop_1deeea75
V_U3 N6 0 DC 5
X_U5 NC_6 CONST0
X_U6 N4 N5 NC_8 NC_7 N3 N4 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U7 NC_9 CONST1 VHIGH=5
X_U8 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 DigitalJKFlipFlop_d1731c79 ActiveLowSetReset=0 NegativeEdgeClock=0 VTH=2.5 VHIGH=5 ClockDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 InitialState=0 RiseDelay=1e-9 FallDelay=1e-9
APROBE_Clk [N5] [d_Clk] AMODEL_Clk
APROBE_Q11 [N7] [d_Q11] AMODEL_Q11
APROBE_Q12 [N3] [d_Q12] AMODEL_Q12

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* Models and supporting definitions follow
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* Toggleable digital constant logic-level source
.subckt TOGGLEABLE_DIGITAL_CONSTANT OUT GND PARAMS: state=0 logicLow=0 logicHigh=5
    BOUT OUT GND V = {logicLow+(logicHigh-logicLow)*state}
.ends TOGGLEABLE_DIGITAL_CONSTANT
.subckt DigitalClock_4e731c5d OUT PARAMS: Frequency=1000 Duty=50 Delay=0
    .param period={1/Frequency}
    .param pulseWidth={Duty*0.01/Frequency}
    VCLK OUT 0 PULSE(0 5 {Delay} 1n 1n {pulseWidth} {period})
.ENDS DigitalClock_4e731c5d
* LED source-variant replacement with current-sense brightness node
.subckt LED_VIRTUAL_b2f33485 T0 T1 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
    DLED T0 SENSE LED_VIRTUAL_b2f33485_DIODE
    .model LED_VIRTUAL_b2f33485_DIODE D(IS={IS} N={N} RS={RS} CJO={CJO} M={M} VJ={VJ} BV={BV} IBV={IBV})
    VSENSE SENSE T1 DC 0
    BLIT lit 0 V = { (i(VSENSE) > {OnCurrent}) ? 1 : ((i(VSENSE) < 0) ? 0 : (i(VSENSE) / {OnCurrent})) }
.ends LED_VIRTUAL_b2f33485
.model DigitalTFlipFlop_1deeea75 d_tff (rise_delay=1n fall_delay=1n clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)
* Constant logic-low source
.subckt CONST0 OUT
    BOUT OUT 0 V = { 0 }
.ends CONST0
* DigitalDFlipFlop_79c3a797 normalized for ngspice-web: analog bridges replace unsupported source polarity helpers.
.subckt DigitalDFlipFlop_79c3a797 1 2 3 4 5 6 params: NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1e-9 FallDelay=1e-9 VTH=2.5 VHIGH=5
    BD_INACTIVE D_INACTIVE 0 V = 0
    RDATA_DEFAULT 1 D_INACTIVE 1G
    BSET_INACTIVE SET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    BRESET_INACTIVE RESET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    RSET_DEFAULT 3 SET_INACTIVE 1G
    RRESET_DEFAULT 4 RESET_INACTIVE 1G
    BCLK_POL CLK_POL 0 V = { (NegativeEdgeClock > 0.5) ? ((V(2) > VTH) ? 0 : VHIGH) : V(2) }
    BSET_POL SET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(3) > VTH) ? 0 : VHIGH) : V(3) }
    BRESET_POL RESET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(4) > VTH) ? 0 : VHIGH) : V(4) }
    .model DigitalDFlipFlop_79c3a797_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model DigitalDFlipFlop_79c3a797_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model DigitalDFlipFlop_79c3a797_CORE d_dff(clk_delay={ClkDelay} set_delay={SetDelay} reset_delay={ResetDelay} ic={Ic} rise_delay={RiseDelay} fall_delay={FallDelay})
    AD [1] [d_data] DigitalDFlipFlop_79c3a797_A2D
    ACLK [CLK_POL] [d_clk] DigitalDFlipFlop_79c3a797_A2D
    ASET [SET_POL] [d_set] DigitalDFlipFlop_79c3a797_A2D
    ARESET [RESET_POL] [d_reset] DigitalDFlipFlop_79c3a797_A2D
    AFF d_data d_clk d_set d_reset d_q d_nq DigitalDFlipFlop_79c3a797_CORE
    AQ [d_q] [5] DigitalDFlipFlop_79c3a797_D2A
    ANQ [d_nq] [6] DigitalDFlipFlop_79c3a797_D2A
.ends DigitalDFlipFlop_79c3a797
* Constant logic-high source
.subckt CONST1 OUT VHIGH=5
    BOUT OUT 0 V = { VHIGH }
.ends CONST1
* JK flip-flop source-variant replacement with analog logic bridges
.subckt DigitalJKFlipFlop_d1731c79 T0 T1 T2 T3 T4 T5 T6 ActiveLowSetReset=0 NegativeEdgeClock=0 ClockDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 InitialState=0 RiseDelay=1e-9 FallDelay=1e-9 VTH=2.5 VHIGH=5
    BCLK_POL CLK_POL 0 V = {(NegativeEdgeClock > 0.5) ? ((V(T2) > VTH) ? 0 : VHIGH) : V(T2)}
    BSET_INACTIVE SET_INACTIVE 0 V = {(ActiveLowSetReset > 0.5) ? VHIGH : 0}
    BRESET_INACTIVE RESET_INACTIVE 0 V = {(ActiveLowSetReset > 0.5) ? VHIGH : 0}
    RSET_DEFAULT T3 SET_INACTIVE 1G
    RRESET_DEFAULT T4 RESET_INACTIVE 1G
    BSET_POL SET_POL 0 V = {(ActiveLowSetReset > 0.5) ? ((V(T3) > VTH) ? 0 : VHIGH) : V(T3)}
    BRESET_POL RESET_POL 0 V = {(ActiveLowSetReset > 0.5) ? ((V(T4) > VTH) ? 0 : VHIGH) : V(T4)}
    .model DigitalJKFlipFlop_d1731c79_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model DigitalJKFlipFlop_d1731c79_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model DigitalJKFlipFlop_d1731c79_CORE d_jkff(clk_delay={ClockDelay} set_delay={SetDelay} reset_delay={ResetDelay} ic={InitialState} rise_delay={RiseDelay} fall_delay={FallDelay})
    AJ [T0] [d_j] DigitalJKFlipFlop_d1731c79_A2D
    AK [T1] [d_k] DigitalJKFlipFlop_d1731c79_A2D
    ACLK [CLK_POL] [d_clk] DigitalJKFlipFlop_d1731c79_A2D
    ASET [SET_POL] [d_set] DigitalJKFlipFlop_d1731c79_A2D
    ARESET [RESET_POL] [d_reset] DigitalJKFlipFlop_d1731c79_A2D
    AFF d_j d_k d_clk d_set d_reset d_q d_nq DigitalJKFlipFlop_d1731c79_CORE
    AQ [d_q] [T5] DigitalJKFlipFlop_d1731c79_D2A
    ANQ [d_nq] [T6] DigitalJKFlipFlop_d1731c79_D2A
.ends DigitalJKFlipFlop_d1731c79
.model AMODEL_Clk adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q11 adc_bridge(in_low=0.9 in_high=2.31)
.model AMODEL_Q12 adc_bridge(in_low=3.3 in_high=3.3)

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* Simulation settings
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.options rshunt=1e12
.options noopalter
.tran 2m 1e12 0 2m
.save V(X_LED2.lit) V(X_LED3.lit)
.end