6_3_3_Universal_Schieberegister_Lsg

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
* net label SIL joins NET_049::component:component-a396195e-141d-449e-af60-a6e8eafe71a4:T0 SIL::node:stub-104
X_DG1 N33 DigitalClock_4e731c5d Frequency=10 Duty=50 Delay=0
V_Dir N13 0 DC 0
V_E1 N32 0 DC 5
V_E2 N21 0 DC 0
V_E3 N22 0 DC 0
V_E4 N23 0 DC 0
V_Load N20 0 DC 0
X_U1 N34 N33 N41 N24 N18 NC_1 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U10 N15 N6 N4 AND2 VHIGH=5 VTH=2.5
X_U11 N18 N13 N5 AND2 VHIGH=5 VTH=2.5
X_U12 N13 N6 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U13 N7 N8 N36 OR2 VHIGH=5 VTH=2.5
X_U14 N17 N9 N7 AND2 VHIGH=5 VTH=2.5
X_U15 N19 N13 N8 AND2 VHIGH=5 VTH=2.5
X_U16 N13 N9 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U17 N10 N11 N37 OR2 VHIGH=5 VTH=2.5
X_U18 N16 N12 N10 AND2 VHIGH=5 VTH=2.5
X_U19 N15 N13 N11 AND2 VHIGH=5 VTH=2.5
X_U2 N35 N33 N40 N25 N19 NC_2 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U20 N13 N12 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U21 N20 N22 N39 AND2 VHIGH=5 VTH=2.5
X_U22 N20 N29 N26 AND2 VHIGH=5 VTH=2.5
X_U23 N32 N31 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U24 N20 N32 N41 AND2 VHIGH=5 VTH=2.5
X_U25 N20 N28 N27 AND2 VHIGH=5 VTH=2.5
X_U26 N21 N30 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U27 N20 N31 N24 AND2 VHIGH=5 VTH=2.5
X_U28 N20 N23 N38 AND2 VHIGH=5 VTH=2.5
X_U29 N22 N29 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U3 N36 N33 N39 N26 N15 NC_3 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=1 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U30 N20 N21 N40 AND2 VHIGH=5 VTH=2.5
X_U31 N20 N30 N25 AND2 VHIGH=5 VTH=2.5
X_U32 N23 N28 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
V_U33 N42 0 DC 0
V_U34 N16 0 DC 5
X_U4 N37 N33 N38 N27 N17 NC_4 DigitalDFlipFlop_79c3a797 NegativeEdgeClock=1 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1n FallDelay=1n
X_U5 N1 N2 N34 OR2 VHIGH=5 VTH=2.5
X_U6 N19 N3 N1 AND2 VHIGH=5 VTH=2.5
X_U7 N14 N13 N2 AND2 VHIGH=5 VTH=2.5
X_U8 N13 N3 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U9 N4 N5 N35 OR2 VHIGH=5 VTH=2.5
APROBE_Clk [N33] [d_Clk] AMODEL_Clk
APROBE_Q1 [N18] [d_Q1] AMODEL_Q1
APROBE_Q2 [N19] [d_Q2] AMODEL_Q2
APROBE_Q3 [N15] [d_Q3] AMODEL_Q3
APROBE_Q4 [N17] [d_Q4] AMODEL_Q4
APROBE_Load [N20] [d_Load] AMODEL_Load

**************************************************
* Models and supporting definitions follow
**************************************************
.subckt DigitalClock_4e731c5d OUT PARAMS: Frequency=1000 Duty=50 Delay=0
    .param period={1/Frequency}
    .param pulseWidth={Duty*0.01/Frequency}
    VCLK OUT 0 PULSE(0 5 {Delay} 1n 1n {pulseWidth} {period})
.ENDS DigitalClock_4e731c5d
* DigitalDFlipFlop_79c3a797 normalized for ngspice-web: analog bridges replace unsupported source polarity helpers.
.subckt DigitalDFlipFlop_79c3a797 1 2 3 4 5 6 params: NegativeEdgeClock=0 NegativeSETRESET=0 ClkDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 Ic=0 RiseDelay=1e-9 FallDelay=1e-9 VTH=2.5 VHIGH=5
    BD_INACTIVE D_INACTIVE 0 V = 0
    RDATA_DEFAULT 1 D_INACTIVE 1G
    BSET_INACTIVE SET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    BRESET_INACTIVE RESET_INACTIVE 0 V = { (NegativeSETRESET > 0.5) ? VHIGH : 0 }
    RSET_DEFAULT 3 SET_INACTIVE 1G
    RRESET_DEFAULT 4 RESET_INACTIVE 1G
    BCLK_POL CLK_POL 0 V = { (NegativeEdgeClock > 0.5) ? ((V(2) > VTH) ? 0 : VHIGH) : V(2) }
    BSET_POL SET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(3) > VTH) ? 0 : VHIGH) : V(3) }
    BRESET_POL RESET_POL 0 V = { (NegativeSETRESET > 0.5) ? ((V(4) > VTH) ? 0 : VHIGH) : V(4) }
    .model DigitalDFlipFlop_79c3a797_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model DigitalDFlipFlop_79c3a797_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model DigitalDFlipFlop_79c3a797_CORE d_dff(clk_delay={ClkDelay} set_delay={SetDelay} reset_delay={ResetDelay} ic={Ic} rise_delay={RiseDelay} fall_delay={FallDelay})
    AD [1] [d_data] DigitalDFlipFlop_79c3a797_A2D
    ACLK [CLK_POL] [d_clk] DigitalDFlipFlop_79c3a797_A2D
    ASET [SET_POL] [d_set] DigitalDFlipFlop_79c3a797_A2D
    ARESET [RESET_POL] [d_reset] DigitalDFlipFlop_79c3a797_A2D
    AFF d_data d_clk d_set d_reset d_q d_nq DigitalDFlipFlop_79c3a797_CORE
    AQ [d_q] [5] DigitalDFlipFlop_79c3a797_D2A
    ANQ [d_nq] [6] DigitalDFlipFlop_79c3a797_D2A
.ends DigitalDFlipFlop_79c3a797
* AND 2-Input gate, ideal behavioral
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH)) ? VHIGH : 0}
.ends AND2
* Generic digital inverter (NOT gate) with normalized propagation delay
.subckt INV IN OUT VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
    BTARGET TARGET 0 V = {(V(IN) > VTH) ? 0 : VHIGH}
    GDELAY STATE 0 VALUE = {(V(TARGET) > V(STATE)) ? (V(STATE)-V(TARGET))/(((RiseDelay > 1e-15) ? RiseDelay : 1e-15)/(0.69314718056*1e-9)) : (V(STATE)-V(TARGET))/(((FallDelay > 1e-15) ? FallDelay : 1e-15)/(0.69314718056*1e-9))}
    CDELAY STATE 0 1n
    BOUT OUT 0 V = {(V(STATE) >= VHIGH/2) ? VHIGH : 0}
.ends INV
* OR 2-Input gate, ideal behavioral
.subckt OR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) || (V(B) > VTH) ? VHIGH : 0}
.ends OR2
.model AMODEL_Clk adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q1 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q2 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q3 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Q4 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_Load adc_bridge(in_low=3.3 in_high=3.3)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.options noopalter
.tran 2m 1e12 0 2m
.save time V(N33) V(N18) V(N19) V(N15) V(N17) V(N20)
.end