JK

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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X_U1 N2 N2 N3 0 0 N4 NC_1 DigitalJKFlipFlop_d1731c79 ActiveLowSetReset=0 NegativeEdgeClock=0 VTH=2.5 VHIGH=5 ClockDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 InitialState=0 RiseDelay=1e-9 FallDelay=1e-9
X_U2 N4 N4 N3 0 0 N1 NC_2 DigitalJKFlipFlop_d1731c79 ActiveLowSetReset=0 NegativeEdgeClock=0 VTH=2.5 VHIGH=5 ClockDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 InitialState=0 RiseDelay=1e-9 FallDelay=1e-9
X_U3 N3 DigitalClock_4e731c5d Frequency=1 Duty=50 Delay=0
V_U4 N2 0 DC 5
APROBE_DP1 [N4] [d_DP1] AMODEL_DP1
APROBE_DP2 [N1] [d_DP2] AMODEL_DP2

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* Models and supporting definitions follow
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* JK flip-flop source-variant replacement with analog logic bridges
.subckt DigitalJKFlipFlop_d1731c79 T0 T1 T2 T3 T4 T5 T6 ActiveLowSetReset=0 NegativeEdgeClock=0 ClockDelay=1e-9 SetDelay=1e-9 ResetDelay=1e-9 InitialState=0 RiseDelay=1e-9 FallDelay=1e-9 VTH=2.5 VHIGH=5
    BCLK_POL CLK_POL 0 V = {(NegativeEdgeClock > 0.5) ? ((V(T2) > VTH) ? 0 : VHIGH) : V(T2)}
    BSET_INACTIVE SET_INACTIVE 0 V = {(ActiveLowSetReset > 0.5) ? VHIGH : 0}
    BRESET_INACTIVE RESET_INACTIVE 0 V = {(ActiveLowSetReset > 0.5) ? VHIGH : 0}
    RSET_DEFAULT T3 SET_INACTIVE 1G
    RRESET_DEFAULT T4 RESET_INACTIVE 1G
    BSET_POL SET_POL 0 V = {(ActiveLowSetReset > 0.5) ? ((V(T3) > VTH) ? 0 : VHIGH) : V(T3)}
    BRESET_POL RESET_POL 0 V = {(ActiveLowSetReset > 0.5) ? ((V(T4) > VTH) ? 0 : VHIGH) : V(T4)}
    .model DigitalJKFlipFlop_d1731c79_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model DigitalJKFlipFlop_d1731c79_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model DigitalJKFlipFlop_d1731c79_CORE d_jkff(clk_delay={ClockDelay} set_delay={SetDelay} reset_delay={ResetDelay} ic={InitialState} rise_delay={RiseDelay} fall_delay={FallDelay})
    AJ [T0] [d_j] DigitalJKFlipFlop_d1731c79_A2D
    AK [T1] [d_k] DigitalJKFlipFlop_d1731c79_A2D
    ACLK [CLK_POL] [d_clk] DigitalJKFlipFlop_d1731c79_A2D
    ASET [SET_POL] [d_set] DigitalJKFlipFlop_d1731c79_A2D
    ARESET [RESET_POL] [d_reset] DigitalJKFlipFlop_d1731c79_A2D
    AFF d_j d_k d_clk d_set d_reset d_q d_nq DigitalJKFlipFlop_d1731c79_CORE
    AQ [d_q] [T5] DigitalJKFlipFlop_d1731c79_D2A
    ANQ [d_nq] [T6] DigitalJKFlipFlop_d1731c79_D2A
.ends DigitalJKFlipFlop_d1731c79
.subckt DigitalClock_4e731c5d OUT PARAMS: Frequency=1000 Duty=50 Delay=0
    .param period={1/Frequency}
    .param pulseWidth={Duty*0.01/Frequency}
    VCLK OUT 0 PULSE(0 5 {Delay} 1n 1n {pulseWidth} {period})
.ENDS DigitalClock_4e731c5d
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)

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* Simulation settings
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.options noopalter
.tran 0.0001 10 0 20u
.save time V(N4) V(N1)
.end