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Common-emitter bias calculator

Find the DC operating point and voltage headroom of a divider-biased NPN amplifier.

Configure

V

Supply voltage

Ω

Upper bias resistance

Ω

Lower bias resistance

Ω

Collector resistance

Ω

Emitter resistance
Advanced inputs

Forward current gain β

Results update as you type.

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Results

Estimated collector current1.29 mA
Collector voltage9.17 V
Emitter voltage1.3 V
Collector–emitter voltage7.87 V
Advanced results
Approximate peak voltage swing2.83 V
Base current12.86 µA
Transistor power10.12 mW

How common-emitter bias works

R1 and R2 set the base bias, R3 is the collector resistor and R4 provides emitter feedback. The calculation includes divider loading by base current. The schematic measures collector and emitter voltage; the usable swing is limited by cutoff and saturation.

IB≈VTH−0.7 VRTH+(β+1)R4I_B\approx\frac{V_{TH}-0.7\,\mathrm V}{R_{TH}+(\beta+1)R_4}

Uses VBE ≈ 0.7 V and VCE(sat) ≈ 0.2 V. The generic transistor simulation uses a nonlinear junction model; bias and headroom are estimates. Inputs must keep the transistor in its active region.

Change the form inputs or click a component value on the schematic. Choose Try in CircuitSim to simulate the configured circuit.