R1 and R2 set the base bias, R3 is the collector resistor and R4 provides emitter feedback. The calculation includes divider loading by base current. The schematic measures collector and emitter voltage; the usable swing is limited by cutoff and saturation.
IB≈RTH+(β+1)R4VTH−0.7V
Uses VBE ≈ 0.7 V and VCE(sat) ≈ 0.2 V. The generic transistor simulation uses a nonlinear junction model; bias and headroom are estimates. Inputs must keep the transistor in its active region.
Change the form inputs or click a component value on the schematic. Choose Try in CircuitSim to simulate the configured circuit.