Voltage Inverter

Use a CMOS clock driver, a flying capacitor, and two diodes to generate a negative supply from a positive supply.

Circuit operation

The CMOS inverter drives flying capacitor CF. D1 clamps its far end near ground on the positive half-cycle; on the negative transition, D2 transfers charge to the output reservoir CO. The output voltage is negative relative to ground.

Expected behavior

$$V_o\approx-(V_{DD}-2V_F)$$ $$\Delta V_o\approx\frac{I_L}{fC_O}$$

The saved clock is 1 kHz, CF is 1 µF, CO is 10 µF, and RL is 100 kΩ. Expect a negative output of a few volts after startup, with diode losses and load sag. The blue current trace is oriented to show the positive magnitude of current delivered to the load from ground.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 20.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set RL to 200 kΩ; the negative output sags less under the lighter load. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The CMOS models use illustrative threshold, transconductance, junction-capacitance and series-resistance parameters. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.